Write operations for a memory may occur responsive to an edge of a memory clock signal. For example, an address decoder decodes an address and raises the appropriate word line responsive to the memory clock signal edge. Similarly, an I/O circuit processes a data bit to drive a pair of bit lines with the appropriate differential voltage (one bit line being driven high and one low depending upon the binary value of the data bit) responsive to the memory clock signal edge. Since conventional address decoding involves considerably more logic, the delay from the clock edge to the word line assertion dominated over the delay from the data bit processing prior to driving the bit lines. Thus, the word line development delay was the critical path such that it was sufficient for a conventional memory to model this delay using a word line tracker. Once the word line tracker had finished modeling the word line development delay, a bit line tracker modeled the delay required to develop a bit line voltage responsive to the assertion of a “dummy” word line in the word line tracker.
The dummy word line is matched to the word line it models so that it has the substantially the same capacitance, resistance, and inductance (the same electrical properties) for the actual word line being modeled. The bit line tracker similarly includes a dummy bit line that also substantially matches the electrical properties for the bit lines. Based upon the delays modeled by the word line tracker and associated bit line tracker, a conventional memory could adjust its write operation timing so that a write operation could be finished successfully from one clock edge to a subsequent clock edge.
However, such traditional memory delay modeling is problematic in modern memory architectures. In particular, it is now routine for the core logic to be powered by an independent power supply rail (denoted herein as “CX”) and for the memory to be powered by another independent power supply rail (denoted herein as “MX”). The CX power supply voltage level is thus independent of the MX power supply voltage level. Such independence saves power because the core logic can retain its state at lower levels for the logic power supply voltage as compared to the lowest level for the memory power supply voltage at which the memory still retains its state. The lower voltage level for the logic power supply voltage reduces leakage current loss and preserves battery life.
Given this logic power domain/memory power domain dichotomy, it is advantageous to push as much of the decoding in the bit line and word line paths into the logic power domain as possible since power consumption is proportional to the square of the power supply voltage. A traditional memory tracking scheme then becomes unfeasible as the location of the critical path with regard to being in the bit line development path or being in the word line development path depends upon the relative power supply voltages in the logic and memory power domains.
Accordingly, there is a need in the art for improved memory tracking architectures.